1. Field of the Invention
The present invention relates in general to a computer-implemented method for debugging a RTL design, and in particular, to a method for debugging a RTL design in an emulation or co-emulation system.
2. Description of the Prior Art
For debugging purposes, it is generally known that emulation and prototyping systems may use logic analyzers to capture signal values at runtime. However, the number of signals that can be captured is limited, typically in the range of tens to hundreds of signals. Given the complexity of today's design, IC designers may need to know the values of most, if not all, signals during debugging. This provides a “full visibility” for debugging or other purposes. Using various techniques, turn-key emulation and prototyping systems may offer full visibility for debugging. For many IC designers, however, they prefer their own in-house prototyping systems over turn-key systems, because the former are tailored to their needs. Furthermore, depending on the designs and systems, certain turn-key systems may be costly, time-consuming, and/or error-prone.
FIG. 1 shows a general flow for in-house built FPGA-based prototyping system. To start, user's RTL design 100 is synthesized into a gate level netlist (block 101). The gate level netlist is then fitted into an emulation system (block 102), which includes one or more FPGA devices. The gate level netlist will be partitioned into multiple netlists, if necessary, so that each can fit in an FPGA device. The partitioned netlist is typically expressed in an industry standard netlist format, such as EDIF. Finally, P&R tools are run to convert each partitioned netlist into an image that can be downloaded to an FPGA device for emulating the design (block 103).
In order to debug a RTL design in an FPGA-based emulation system while considering the limited resources in the emulation system, one must determine what signals in the RTL design are most relevant or essential for trouble-shooting a particular bug. However, all the signal names in RTL are in a hierarchical form which is not efficient for synthesizing and fitting process later on; therefore, it is more convenient to maintain the signal names in a flattened form to cut short the length of each signal name to speed up the synthesizing and fitting process. Since there in no direct meaning in names of gate-level signals, names of gate-level signals are not readable and correlated to signals names in a RTL design after synthesizing.
Therefore, what is needed is a solution to provide full or improved visibility of signals in a RTL design when the RTL design is debugged using an emulation system.